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VR4102 Datasheet(PDF) 260 Page - NEC |
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VR4102 Datasheet(HTML) 260 Page - NEC |
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260 / 701 page  CHAPTER 10 BCU (BUS CONTROL UNIT) 260 Figure 10-11. 2-byte Access when Sampling ZWS# at Low Level on 8-bit Bus (WISAA[2:0] = 101) Tisa Tisa Tisa Tisa TClock(Internal) ADD[25:0] IOCS16# MEMCS16# IOR#/IOW# MEMR#/MEMW# IOCHRDY ZWS# DATA[15:0] (Write) DATA[15:0] (Read) Remark The dotted lines indicate high impedance. (2) Bus Operations in High-Speed System Bus The space of physical address from 0x0A00 0000 to 0x0AFF FFFF can be used as the high-speed system bus memory space by setting the ISAM/LCD bit of BCUCNTREG1. WLCD/M [2:0] (BCUSPEEDREG [10:8]) can be used to set the access time for access to this space, as shown in the table below. Table 10-11. High-Speed System Bus Access Times WLCD/W [2:0] Tisa (TClock) 000 8 001 7 010 6 011 5 100 4 101 3 110 2 111 1 |
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