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VR4102 Datasheet(PDF) 491 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 491 Page - NEC

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CHAPTER 25 HSP (MODEM INTERFACE UNIT)
491
(7) HSPSTS (0x0C00 0022: Index 1, Read)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
Undefined
Undefined
Undefined
Other resets
0
0
0
0
0
Undefined
Undefined
Undefined
Bit
D7
D6D5
D4D3D2
D1
D0
Name
AFESEL1
AFESEL0
IBYTE
TO
CFGCP
IRQS
RxOVRUN
TxUDRUN
R/W
R
RR
RRR
R
R
RTCRST
Undefined
Undefined
Undefined
0
0
0
0
0
Other resets
Undefined
Undefined
Undefined
0
0
0
0
0
Bit
Name
Function
D[15:8]
Reserved
0 is returned after read.
D[7:6]
AFESEL[1:0]
Indicates the AFESEL[1:0] signal (internal) state
D[5]
IBYTE
Indicates the BYTE signal (internal) state
D[4]
TO
Error-related timeout
1 : Timeout occurred
0 : No timeout
D[3]
CFGCP
CODEC configuration complete
1 : Complete
0 : Not complete
D[2]
IRQS
Pending interrupt exists
1 : Exists
0 : No pending interrupts
D[1]
RxOVRUN
Receive overrun occurred
1 : Occurred
0 : No receive overruns
D[0]
TxUDRUN
Transmit underrun occurred
1 : Occurred
0 : No transmit overruns
This register is used to indicate the status in communication when the INDEX number is 1.
TO bit is set (to “1”) when the timeout counter reaches the value specified by the TOC bit of HSPTOC register.
CFGCP bit indicates whether or not CODEC initialization has been completed. Actually, this bit is set (to “1”)
when the START bit of HSPCNTL register has been set as active to reset the FIFO pointer and then 9-word data
has been transmitted (1 word = 16 bits).
IRQS bit indicates whether or not any pending interrupt exists. When an interrupt request from HSP to the CPU
core is in pending, the request is cleared after this register is read.
IRQS, RxOVRUN, TxUDRUN bits are cleared (to “0”) when read.



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