VR4102 datasheet(488/701 Pages) NEC

488 / 701 page

CHAPTER 25 HSP (MODEM INTERFACE UNIT)

488

(4) HSPTOC and HSPMCLKD (0x0C00 0022: Index 3, Write)

Bit

D15

D14

D13

D12

D11

D10

Name

Reserved

TOC3

TOC2

TOC1

TOC0

R/W

WWW

RTCRST

Undefined

Other resets

Undefined

Bit

D6D5

D4D3D2

Name

Reserved

MCLKD4

MCLKD3

MCLKD2

MCLKD1

MCLKD0

R/W

WWW

RTCRST

Undefined

Other resets

Undefined

Bit

Name

Function

D[15:12]

Reserved

Write 0 when writing.

D[11:8]

TOC[3:0]

High-order 4 bits of timeout count

D[7:5]

Reserved

Write 0 when writing.

D[4:0]

MCLKD[4:0]

HSPMCLK divisor to clock input

HSPMCLK frequency = 18.432 MHz / (MCLKD[4:0] + 2)

The upper byte of this register sets the timeout counter value and lower byte sets the HSPMCLK’s division ratio

when the INDEX number is 3.

TOC[3:0] is used to set the high-order four bits of the final count of the timeout counter. The timeout counter is a

12-bit counter and is incremented once for each interrupt signal that is not serviced. The low-order 8 bits are

automatically set to 0 when TOC[3:0] is set. When the specified timeout count value is reached, TO bit of

HSPSTS register is set to 1. The user is responsible for resetting the HSP core to prevent a system hang-up.

MCLKD[4:0] is used to set the division ratio when the 18.432-MHz clock supplied to HSPMCLK pin can be

output using a programmable division ratio. If MCLKD[4:0] is “0”, there is no clock division and the 18.432-MHz

clock is output. Note that an even number must be set to MCLKD[4:0].

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