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VR4102 Datasheet(PDF) 486 Page - NEC |
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VR4102 Datasheet(HTML) 486 Page - NEC |
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486 / 701 page ![]() CHAPTER 25 HSP (MODEM INTERFACE UNIT) 486 (2) HSPCNTL (0x0C00 0022: Index 1, Write) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W W WW WWW W W RTCRST 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Other resets 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Bit D7 D6D5 D4D3D2 D1 D0 Name NTORST ENIRQ START Reserved ENTX IRQS2 IRQS1 IRQS0 R/W W WW WWW W W RTCRST 00 00 0 0 0 0 Other resets 00 00 0 0 0 0 Bit Name Function D[15:8] Reserved Write 0 when writing. D[7] NTORST Disable timeout reset When this bit is “0”, it enables a timeout to occur when a specified number of errors have been counted, at which point the HSP resets itself. 1 : Disable 0 : Enable D[6] ENIRQ Interrupt enable 1 : Enable 0 : Disable D[5] START RX/TX FIFO pointer initialization When this bit is set to “1”, the RX/TX FIFO pointer is set to its initial position. 1 : Initialize (at rising edge) 0 : Status hold D[4] Reserved Write 0 when writing. D[3] ENTX Transfer enable 1 : Enable 0 : Disable D[2:0] IRQS[2:0] Interrupt signal select. However, IRQ signal is always selected whatever value is set to these bits. Caution If 1 is set to ENTX bit, the only way to stop the operation is by resetting the HSP unit. |
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