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VR4102 Datasheet(PDF) 578 Page - NEC |
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VR4102 Datasheet(HTML) 578 Page - NEC |
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578 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 578 DSRA Doubleword Shift Right Arithmetic DSRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSRA 1 1 1 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 0 || sa GPR [rd] <- (GPR [rt]63) s || GPR [rt] 63..s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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