VR4102 datasheet(574/701 Pages) NEC

574 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

574

DMULTU

Doubleword Multiply Unsigned

DMULTU

SPECIAL

0 0 0 0 0 0

0 0

0 0 0 0

26 25

21 20

16 15

DMULTU

0 1 1 1 0 1

Format:

DMULTU rs, rt

Description:

The contents of general register

rs and the contents of general register rt are multiplied, treating both operands as

unsigned values. No overflow exception occurs under any circumstances.

When the operation completes, the low-order word of the double result is loaded into special register

LO, and the

high-order word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by a minimum of two instructions.

This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user

or supervisor mode causes a reserved instruction exception.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]) * (0 || GPR [rt])

<- t63..0

<- t127..64

Exceptions:

Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)

VR4102 Datasheet(PDF) 574 Page - NEC