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VR4102 Datasheet(PDF) 571 Page - NEC |
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VR4102 Datasheet(HTML) 571 Page - NEC |
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571 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 571 DMFC0 Doubleword Move From System Control Coprocessor DMFC0 DMF 0 0 0 0 1 COP0 0 1 0 0 0 0 rt rd 31 26 25 21 20 16 15 0 6 555 0 0 0 0 0 0 0 0 0 0 0 0 11 10 11 Format: DMFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. This operation is defined for the VR4102 operating in 64-bit mode and in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. All 64-bits of the general register destination are written from the coprocessor register source. The operation of DMFC0 on a 32-bit coprocessor 0 register is undefined. Operation: 64 T: data <- CPR [0, rd] T+1: GPR [rt] <- data Exceptions: Coprocessor unusable exception (user mode and supervisor mode if CP0 not enabled) Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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