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VR4102 Datasheet(PDF) 575 Page - NEC |
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VR4102 Datasheet(HTML) 575 Page - NEC |
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575 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 575 DSLL Doubleword Shift Left Logical DSLL 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa DSLL 1 1 1 0 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DSLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits. The result is placed in register rd. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: s <- 0 || sa GPR [rd] <- GPR [rt](63 - s)..0 || 0 s Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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