VR4102 datasheet(569/701 Pages) NEC

569 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

569

DMADD16 Doubleword Multiply and Add 16-bit integer DMADD16

SPECIAL

0 0 0 0 0 0

0 0

0 0 0 0

26 25

21 20

16 15

DMADD16

1 0 1 0 0 1

Format:

DMADD16 rs, rt

Description:

The contents of general registers

rs and rt are multiplied, treating both operands as 16-bit 2’s complement values.

The operand[62:15] must be valid 15-bit, sign-extended values. If not, the result is unpredictable.

This multiplied result and the 64-bit data joined of special register

LO is added to form the result as a signed

integer. When the operation completes, the doubleword result is loaded into special register

LO.

No integer overflow exception occurs under any circumstances.

This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user

or supervisor mode causes a reserved instruction exception.

The following table shows hazard cycles between DMADD16 and other instructions.

Instruction sequence

No. of cycles

MULT/MULTU -> DMADD16

1 Cycle

DMULT/DMULTU -> DMADD16

4 Cycles

DIV/DIVU -> DMADD16

36 Cycles

DDIV/DDIVU -> DMADD16

68 Cycles

MFHI/MFLO -> DMADD16

2 Cycles

MADD16 -> DMADD16

0 Cycles

DMADD16 -> DMADD16

0 Cycles

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