VR4102 datasheet(565/701 Pages) NEC

565 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

565

DDIV

Doubleword Divide

DDIV

SPECIAL

0 0 0 0 0 0

0 0

0 0 0 0

DDIV

0 1 1 1 1 0

26 25

21 20

16 15

6 5

Format:

DDIV rs, rt

Description:

The contents of general register

rs are divided by the contents of general register rt, treating both operands as 2’s

complement values. No overflow exception occurs under any circumstances, and the result of this operation is

undefined when the divisor is zero.

This instruction is typically followed by additional instructions to check for a zero divisor and for overflow.

When the operation completes, the quotient word of the double result is loaded into special register LO, and the

remainder word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by two or more instructions. This is defined in

this manner to take account of the VR4000TM hazards (for code compatibility) as well as the VR4100’s own

hazards.

This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user

or supervisor mode causes a reserved instruction exception.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- GPR [rs] div GPR [rt]

<- GPR [rs] mod GPR [rt]

Exceptions:

Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)

VR4102 Datasheet(PDF) 565 Page - NEC

VR4102 Datasheet(HTML) 565 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL