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VR4102 Datasheet(PDF) 564 Page - NEC |
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VR4102 Datasheet(HTML) 564 Page - NEC |
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564 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 564 DADDU Doubleword Add Unsigned DADDU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADDU 1 0 1 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. No overflow exception occurs under any circumstances. The only difference between this instruction and the DADD instruction is that DADDU never causes an overflow exception. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] + GPR [rt] Exceptions: Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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