VR4102 datasheet(566/701 Pages) NEC

566 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

566

DDIVU

Doubleword Divide Unsigned

DDIVU

SPECIAL

0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

26 25

21 20

16 15

DDIVU

0 1 1 1 1 1

Format:

DDIVU rs, rt

Description:

The contents of general register

rs are divided by the contents of general register rt, treating both operands as

unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation

is undefined when the divisor is zero.

This instruction may be followed by additional instructions to check for a zero divisor, inserted by the programmer.

When the operation completes, the quotient word of the double result is loaded into special register

LO, and the

remainder word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by two or more instructions.

This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user

or supervisor mode causes a reserved instruction exception.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]) div (0 || GPR [rt])

<- (0 || GPR [rs]) mod (0 || GPR [rt])

Exceptions:

Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)

VR4102 Datasheet(PDF) 566 Page - NEC