VR4102 datasheet(568/701 Pages) NEC

568 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

568

DIVU

Divide Unsigned

DIVU

SPECIAL

0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

26 25

21 20

16 15

DIVU

0 1 1 0 1 1

Format:

DIVU rs, rt

Description:

The contents of general register

rs are divided by the contents of general register rt, treating both operands as

unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation

is undefined when the divisor is zero.

In 64-bit mode, the operands must be valid sign-extended, 32-bit values.

This instruction is typically followed by additional instructions to check for a zero divisor.

When the operation completes, the quotient word of the double result is loaded into special register LO, and the

remainder word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by two or more instructions.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]) div (0 || GPR [rt])

<- (0 || GPR [rs]) mod (0 || GPR [rt])

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]31..0) div (0 || GPR [rt]31..0)

<- (0 || GPR [rs]31..0) mod (0 || GPR [rt]31..0)

<- (q31)

32 || q31..0

<- (r31)

32 || r31..0

Exceptions:

None

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