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VR4102 Datasheet(PDF) 561 Page - NEC |
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VR4102 Datasheet(HTML) 561 Page - NEC |
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561 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 561 DADD Doubleword Add DADD rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 DADD 1 0 1 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: DADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd. An overflow exception occurs if the carries out of bits 62 and 63 differ (2’s complement overflow). The destination register rd is not modified when an integer overflow exception occurs. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: GPR [rd] <- GPR [rs] + GPR [rt] Exceptions: Integer overflow exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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