VR4102 datasheet(558/701 Pages) NEC

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VR4102 Datasheet(PDF) 558 Page - NEC

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CHAPTER 27 CPU INSTRUCTION SET DETAILS

558

CACHE

Cache

CACHE

(Continued)

Write back from a primary cache goes to memory. The address to be written is specified by the cache tag and

not the translated physical address.

TLB Refill and TLB Invalid exceptions can occur on any operation. For Index operations (where the physical

address is used to index the cache but need not match the cache tag) unmapped addresses may be used to

avoid TLB exceptions. This operation never causes a TLB Modified exception.

Bits 17...16 of the instruction specify the cache as follows:

Code

Name

Cache

Primary instruction

Primary data

2, 3

Reserved (undefined)

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