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VR4102 Datasheet(PDF) 555 Page - NEC |
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VR4102 Datasheet(HTML) 555 Page - NEC |
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555 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 555 BNEL Branch On Not Equal Likely BNEL rs BNEL 0 1 0 1 0 1 rt offset 31 26 25 21 20 16 15 0 65 5 16 Format: BNEL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general register rt are compared. If the two registers are not equal, then the program branches to the target address, with a delay of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified. Operation: 32 T: target <- (offset15) 14 || offset || 02 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif 64 T: target <- (offset15) 46 || offset || 02 condition <- (GPR [rs] z GPR [rt]) T+1: if condition then PC <- PC + target else NullifyCurrentInstruction endif Exceptions: None |
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