VR4102 datasheet(559/701 Pages) NEC

559 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

559

CACHE

Cache

CACHE

(Continued)

Bits 20...18 (this value is listed under the Code column) of the instruction specify the operation as follows:

Code

Cache

Name

Operation

Index_Invalidate

Set the cache state of the cache block to Invalid.

Index_Write_Back

Invalidate

Examine the cache state and W bit of the primary data cache block at the index

specified by the virtual address. If the state is not Invalid and the W bit is set, then

write back the block to memory. The address to write is taken from the primary

cache tag. Set cache state of primary cache block to Invalid.

I, D

Index_Load_Tag

Read the tag for the cache block at the specified index and place it into the TagLo

CP0 registers, ignoring parity errors. Also load the data parity bits into the ECC

I, D

Index_Store_Tag

Write the tag for the cache block at the specified index from the TagLo and TagHi

CP0 registers.

Create_Dirty_

Exclusive

This operation is used to avoid loading data needlessly from memory when writing

new contents into an entire cache block. If the cache block does not contain the

specified address, and the block is dirty, write it back to the memory. In all cases,

set the cache state to Dirty.

I, D

Hit_Invalidate

If the cache block contains the specified address, mark the cache block invalid.

Hit_Write_Back

Invalidate

If the cache block contains the specified address, write back the data if it is dirty, and

mark the cache block invalid.

Fill

Fill the primary instruction cache block from memory. If the CE bit of the Status

parity bits for addressed doubleword when written to the instruction cache.

Hit_Write_Back

If the cache block contains the specified address and the W bit is set, write back the

data to memory and clear the W bit.

Hit_Write_Back

If the cache block contains the specified address, write back the data unconditionally.

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