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VR4102 Datasheet(PDF) 586 Page - NEC |
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VR4102 Datasheet(HTML) 586 Page - NEC |
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586 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 586 ERET Exception Return ERET CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERET 0 1 1 0 0 0 31 26 25 24 6 5 0 61 19 6 Format: ERET Description: ERET is the VR4102 instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction, ERET does not execute the next instruction. ERET must not itself be placed in a branch delay slot. If the processor is servicing an error trap (SR2 = 1), then load the PC from the ErrorEPC register and clear the ERL bit of the Status register (SR2). Otherwise (SR2 = 0), load the PC from the EPC register, and clear the EXL bit of the Status register ( SR1). Operation: 32, 64 T: if SR2 = 1 then PC <- ErrorEPC SR <- SR31..3 || 0 || SR1..0 else PC <-EPC SR <- SR31..2 || 0 || SR0 endif Exceptions: Coprocessor unusable exception |
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