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VR4102 Datasheet(PDF) 587 Page - NEC |
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VR4102 Datasheet(HTML) 587 Page - NEC |
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587 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 587 HIBERNATE Hibernate HIBERNATE CO 1 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIBERNATE 1 0 0 0 1 1 31 26 25 24 6 5 0 61 19 6 Format: HIBERNATE Description: HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode. When the HIBERNATE instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline. Once the VR4102 is in Hibernate mode, the Cold Reset sequence will cause the VR4102 to exit Hibernate mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Hibernate operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. |
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