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VR4102 Datasheet(PDF) 591 Page - NEC |
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VR4102 Datasheet(HTML) 591 Page - NEC |
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591 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 591 JR Jump Register JR rs SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 0 65 15 JR 0 0 1 0 0 0 65 6 Format: JR rs Description: The program unconditionally jumps to the address contained in general register rs, with a delay of one instruction. Since instructions must be word-aligned, a Jump Register instruction must specify a target register ( rs) which contains an address whose two low-order bits are zero. If these low-order bits are not zero, an address error exception will occur when the jump target instruction is subsequently fetched. Operation: 32,64 T: temp <- GPR [rs] T+1: PC <- temp Exceptions: None |
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