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VR4102 Datasheet(PDF) 594 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 594 Page - NEC

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CHAPTER 27 CPU INSTRUCTION SET DETAILS
594
LD
Load Doubleword
LD
base
LD
1 1 0 1 1 1
rt
offset
31
26 25
21 20
16 15
0
65
5
16
Format:
LD rt, offset (base)
Description:
The 16-bit
offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into
general register
rt.
If any of the three least-significant bits of the effective address are non-zero, an address error exception occurs.
This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user
or supervisor mode causes a reserved instruction exception.
Operation:
64
T:
vAddr <- ((offset15)
48
|| offset15..0) + GPR [base]
(pAddr, uncached) <- AddressTranslation (vAddr, DATA)
data <- LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR [rt] <- data
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)



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