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VR4102 Datasheet(PDF) 597 Page - NEC |
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VR4102 Datasheet(HTML) 597 Page - NEC |
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597 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 597 LDL Load Doubleword Left LDL (Continued) Given a doubleword in a register and a doubleword in memory, the operation of LDL is as follows: B C D E F G A H J K L M N O I P Register Memory LDL vAddr 2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 PB C D E F G H OP C D E F G H NOP D E F GH MN O P E F G H LM N O P F G H KL M N O P G H JK L M N O P H IJ K L M N O P 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LEM Little-endian memory (BigEndianMem = 0) Type AccessType (see Table 3-2) sent to memory Offset pAddr 2..0 sent to memory Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode) |
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