 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VR4102 Datasheet(PDF) 596 Page - NEC |
|
|
|||||||||||||||||||||||||||||
VR4102 Datasheet(HTML) 596 Page - NEC |
|
|
596 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 596 LDL Load Doubleword Left LDL (Continued) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDL (or LDR) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset 15..0) + GPR [base] (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian 3) if BigEndianMem = 0 then pAddr <- pAddrPSIZE - 1..3 || 0 3 endif byte <- vAddr2..0 xor BigEndianCPU 3 mem <- LoadMemory (uncached, byte, pAddr, vAddr, DATA) GPR [rt] <- mem7 + 8* byte..0 || GPR [rt]55 - 8* byte..0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
