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VR4102 Datasheet(PDF) 599 Page - NEC |
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VR4102 Datasheet(HTML) 599 Page - NEC |
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599 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 599 LDR Load Doubleword Right LDR (Continued) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDR (or LDL) instruction which also specifies register rt. No address error exceptions due to alignment are possible. This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception. Operation: 64 T: vAddr <- ((offset15) 48 || offset15..0) + GPR [base] (pAddr, uncached) <- AddressTranslation (vAddr, DATA) pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian 3 ) if BigEndianMem = 1 then pAddr <- pAddrPSIZE - 1..3 || 0 3 endif byte <- vAddr2..0 xor BigEndianCPU 3 mem <- LoadMemory (uncached, DOUBLEWORD-byte, pAddr, vAddr, DATA) GPR [rt] <- GPR [rt]63..64 – 8 * byte || mem63..8 * byte |
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