VR4102 datasheet(601/701 Pages) NEC

601 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

601

Load Halfword

base

1 0 0 0 0 1

offset

26 25

21 20

16 15

Format:

LH rt, offset (base)

Description:

The 16-bit

offset is sign-extended and added to the contents of general register base to form a virtual address.

The contents of the halfword at the memory location specified by the effective address are sign-extended and

loaded into general register

rt.

If the least-significant bit of the effective address is non-zero, an address error exception occurs.

Operation:

vAddr <- ((offset15)

16 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian

2 || 0))

mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)

byte <- vAddr2...0 xor (BigEndianCPU

2 || 0)

GPR [rt] <- (mem15 + 8 * byte)

16 || mem15 + 8 * byte...8 * byte

vAddr <- ((offset15)

48 || offset

15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian

2 || 0))

mem <- LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)

byte <- vAddr2...0 xor (BigEndianCPU

2 || 0)

GPR [rt] <- (mem15 + 8 * byte)

48 || mem

15 + 8 * byte...8 * byte

Exceptions:

TLB refill exception

TLB invalid exception

Bus error exception

Address error exception

VR4102 Datasheet(PDF) 601 Page - NEC

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