VR4102 datasheet(605/701 Pages) NEC

605 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

605

LWL

Load Word Left

LWL

base

LWL

1 0 0 0 1 0

offset

26 25

21 20

16 15

Format:

LWL rt, offset (base)

Description:

This instruction can be used in combination with the LWR instruction to load a register with four consecutive bytes

from memory, when the bytes cross a word boundary.

LWL loads the left portion of the register with the

appropriate part of the high-order word; LWR loads the right portion of the register with the appropriate part of the

low-order word.

The LWL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual

address which can specify an arbitrary byte. It reads bytes only from the word in memory which contains the

specified starting byte. From one to four bytes will be loaded, depending on the starting byte specified. In 64-bit

mode, the loaded word is sign-extended.

Conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of

the register; then it loads bytes from memory into the register until it reaches the low-order byte of the word in

memory. The least-significant (right-most) byte(s) of the register will not be changed.

address 4

address 0

memory

before

after

$24

LWL $24, 4 ($0)

VR4102 Datasheet(PDF) 605 Page - NEC