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VR4102 Datasheet(PDF) 607 Page - NEC |
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VR4102 Datasheet(HTML) 607 Page - NEC |
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607 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 607 LWL Load Word Left LWL (Continued) Given a doubleword in a register and a doubleword in memory, the operation of LWL is as follows: B C D E F G A H J K L M N O I P Register Memory LWL vAddr 2..0 BigEndianCPU = 0 destination type offset (LEM) 0 1 2 3 4 5 6 7 S S SSP F G H SS S S O P G H SS S S N O P H SS S S M N O P SS S S L F G H S S SSK L G H SS S S J K L H SS S S I J K L 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 LEM Little-endian memory (BigEndianMem = 0) Type AccessType (see Table 3-2) sent to memory Offset pAddr 2...0 sent to memory S sign-extend of destination 31 Exceptions: TLB refill exception TLB invalid exception Bus error exception Address error exception |
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