VR4102 datasheet(608/701 Pages) NEC

608 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

608

LWR

Load Word Right

LWR

base

LWR

1 0 0 1 1 0

offset

26 25

21 20

16 15

Format:

LWR rt, offset (base)

Description:

This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes

from memory, when the bytes cross a word boundary.

LWR loads the right portion of the register with the

appropriate part of the low-order word; LWL loads the left portion of the register with the appropriate part of the

high-order word.

The LWR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual

address which can specify an arbitrary byte. It reads bytes only from the word in memory which contains the

specified starting byte. From one to four bytes will be loaded, depending on the starting byte specified. In 64-bit

mode, the loaded word is sign-extended.

Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of

the register; then it loads bytes from memory into the register until it reaches the high-order byte of the word in

memory. The most significant (left-most) byte(s) of the register will not be changed.

address 4

address 0

memory

before

after

$24

LWR $24, 1 ($0)

$24

VR4102 Datasheet(PDF) 608 Page - NEC