VR4102 datasheet(612/701 Pages) NEC

612 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

612

MADD16

Multiply and Add 16-bit integer

MADD16

SPECIAL

0 0 0 0 0 0

0 0

0 0 0 0

26 25

21 20

16 15

DMADD16

1 0 1 0 0 0

Format:

MADD16 rs, rt

Description:

The contents of general registers

rs and rt are multiplied, treating both operands as 16-bit 2’s complement values.

The operand[62:15] must be valid 15-bit, sign-extended values. If not, the results is unpredictable.

This multiplied result and the 64-bit data joined special register

HI to LO are added to form the result.

No integer overflow exception occurs under any circumstances.

When the operation completes, the low-order word of the double result is loaded into special register

LO, and the

high-order word of the double result is loaded into special register

HI.

The following Table are hazard cycles between MADD16 and other instructions.

Instruction sequence

No. of cycles

MULT/MULTU -> MADD16

1 Cycle

DMULT/DMULTU -> MADD16

4 Cycles

DIV/DIVU -> MADD16

36 Cycles

DDIV/DDIVU -> MADD16

68 Cycles

MFHI/MFLO -> MADD16

2 Cycles

DMADD16 -> MADD16

0 Cycles

MADD16 -> MADD16

0 Cycles

Operation:

32, 64 T:

temp1<- GPR [rs] * GPR [rt]

temp2<- temp1 + (HI31...0 || LO31...0)

<- (temp131)

32 || temp231...0

<- (temp263)

32 || temp263...32

Exceptions:

None

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