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VR4102 Datasheet(PDF) 613 Page - NEC |
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VR4102 Datasheet(HTML) 613 Page - NEC |
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613 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 613 MFC0 Move From System Control Coprocessor MFC0 MF 0 0 0 0 0 COP0 0 1 0 0 0 0 rt 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 555 11 10 11 rd Format: MFC0 rt, rd Description: The contents of coprocessor register rd of the CP0 are loaded into general register rt. When using a register used by the MFC0 by means of instructions before and after it, refer to Chapter 28 and place the instructions in the appropriate location. Operation: 32 T: data <- CPR [0, rd] T+1: GPR [rt] <- data 64 T: data <- CPR [0, rd] T+1: GPR [rt] <- (data31) 32 || data31...0 Exceptions: Coprocessor unusable exception (user and supervisor mode if CP0 not enabled) |
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