VR4102 datasheet(611/701 Pages) NEC

611 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

611

LWU

Load Word Unsigned

LWU

base

LWU

1 0 1 1 1 1

offset

26 25

21 20

16 15

Format:

LWU rt, offset (base)

Description:

The 16-bit

offset is sign-extended and added to the contents of general register base to form a virtual address.

The contents of the word at the memory location specified by the effective address are loaded into general

rt. The loaded word is zero-extended.

If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.

This operation is only defined for the VR4102 operating in 64-bit mode. Execution of this instruction in 32-bit user

or supervisor mode causes a reserved instruction exception.

Operation:

vAddr <- ((offset15)

|| offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0

))

mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA)

byte <- vAddr2...0 xor (BigEndianCPU || 0

GPR [rt] <- 0

32 || mem31 + 8 * byte...8 * byte

vAddr <- ((offset15)

48 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian || 0

2))

mem <- LoadMemory (uncached, WORD, pAddr, vAddr, DATA)

byte <- vAddr2...0 xor (BigEndianCPU || 0

GPR [rt] <- 0

32 || mem31 + 8 * byte...8 * byte

Exceptions:

TLB refill exception

TLB invalid exception

Bus error exception

Address error exception

Reserved instruction exception (VR4102 in 32-bit user mode, VR4102 in 32-bit supervisor mode)

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