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VR4102 Datasheet(PDF) 615 Page - NEC |
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VR4102 Datasheet(HTML) 615 Page - NEC |
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615 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 615 MFLO Move From LO MFLO 0 0 0 0 0 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 31 26 25 11 10 16 15 0 610 5 6 rd 0 0 0 0 0 0 MFLO 0 1 0 0 1 0 5 65 Format: MFLO rd Description: The contents of special register LO are loaded into general register rd. To ensure proper operation in the event of interruptions, the two instructions which follow a MFLO instruction may not be any of the instructions which modify the LO register: MULT, MULTU, DIV, DIVU, MTLO, DMULT, DMULTU, DDIV, DDIVU. Operation: 32, 64 T: GPR [rd] <- LO Exceptions: None |
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