VR4102 datasheet(619/701 Pages) NEC

619 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

619

MULT

Multiply

MULT

SPECIAL

0 0 0 0 0 0

MULT

0 1 1 0 0 0

0 0

0 0 0 0

26 25

21 20

6 5

16 15

Format:

MULT rs, rt

Description:

The contents of general registers

rs and rt are multiplied, treating both operands as 32-bit 2’s complement values.

No integer overflow exception occurs under any circumstances. In 64-bit mode, the operands must be valid 32-

bit, sign-extended values.

When the operation completes, the low-order word of the double result is loaded into special register

LO, and the

high-order word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by a minimum of two other instructions.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- GPR [rs] * GPR [rt]

<- t31...0

<- t63...32

T-2:

<- undefined

T-1:

<- undefined

<- GPR [rs]31...0 * GPR [rt]31...0

<- (t31)

|| t31...0

<- (t63)

|| t63...32

Exceptions:

None

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