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VR4102 Datasheet(PDF) 616 Page - NEC |
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VR4102 Datasheet(HTML) 616 Page - NEC |
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616 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 616 MTC0 Move To Coprocessor0 MTC0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 31 26 25 11 10 16 15 0 6 11 5 5 rt rd MT 0 0 1 0 0 5 21 20 Format: MTC0 rt, rd Description: The contents of general register rt are loaded into coprocessor register rd of coprocessor 0. Because the state of the virtual address translation system may be altered by this instruction, the operation of load instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined. When using a register used by the MTC0 by means of instructions before and after it, refer to Chapter 28 and place the instructions in the appropriate location. Operation: 32, 64 T: data <- GPR [rt] T+1: CPR [0, rd] <- data Exceptions: Coprocessor unusable exception (user and supervisor mode if CP0 not enabled) |
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