VR4102 datasheet(620/701 Pages) NEC

620 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

620

MULTU

Multiply Unsigned

MULTU

SPECIAL

0 0 0 0 0 0

MULTU

0 1 1 0 0 1

0 0

0 0 0 0

26 25

21 20

6 5

16 15

Format:

MULTU rs, rt

Description:

The contents of general register

rs and the contents of general register rt are multiplied, treating both operands as

unsigned values. No overflow exception occurs under any circumstances. In 64-bit mode, the operands must be

valid 32-bit, sign-extended values.

When the operation completes, the low-order word of the double result is loaded into special register

LO, and the

high-order word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined.

Correct operation requires separating reads of

HI or LO from writes by a minimum of two instructions.

Operation:

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]) * (0 || GPR [rt])

<- t31...0

<- t63...32

T-2:

<- undefined

T-1:

<- undefined

<- (0 || GPR [rs]31...0) * (0 || GPR [rt]31...0)

<- (t31)

32 || t

31...0

<- (t63)

32 || t

63...32

Exceptions:

None

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