VR4102 datasheet(624/701 Pages) NEC

624 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

624

Store Byte

base

1 0 1 0 0 0

offset

26 25

21 20

16 15

Format:

SB rt, offset (base)

Description:

The 16-bit

offset is sign-extended and added to the contents of general register base to form a virtual address.

The least-significant byte of register

rt is stored at the effective address.

Operation:

vAddr <- ((offset15)

16 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian

3))

byte <- vAddr2...0 xor BigEndianCPU

data <- GPR [rt]63 – 8 * byte...0 || 0

8 * byte

StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)

vAddr <- ((offset15)

48 || offset

15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor (ReverseEndian

3))

byte <- vAddr2...0 xor BigEndianCPU

data <- GPR [rt]63 – 8 * byte...0 || 0

8 * byte

StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)

Exceptions:

TLB refill exception

TLB invalid exception

TLB modification exception

Bus error exception

Address error exception

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