VR4102 datasheet(606/701 Pages) NEC

606 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

606

LWL

Load Word Left

LWL

(Continued)

The contents of general register

rt are internally bypassed within the processor so that no NOP is needed

between an immediately preceding load instruction which specifies register

rt and a following LWL (or LWR)

instruction which also specifies register

rt.

No address error exceptions due to alignment are possible.

Operation:

vAddr <- ((offset15)

16 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

if BigEndianMem = 0 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

word <- vAddr2 xor BigEndianCPU

mem <- LoadMemory (uncached, byte, pAddr, vAddr, DATA)

temp <- mem32 * word + 8 * byte + 7...32 * word || GPR [rt]23 – 8 * byte...0

GPR [rt] <- temp

vAddr <- ((offset15)

48 || offset

15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

if BigEndianMem = 0 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

word <- vAddr2 xor BigEndianCPU

mem <- LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)

temp <- mem32 * word + 8 * byte + 7...32 * word || GPR [rt]23 – 8 * byte...0

GPR [rt] <- (temp31)

32 || temp

VR4102 Datasheet(PDF) 606 Page - NEC