VR4102 datasheet(598/701 Pages) NEC

598 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

598

LDR

Load Doubleword Right

LDR

base

LDR

0 1 1 0 1 1

offset

26 25

21 20

16 15

Format:

LDR rt, offset (base)

Description:

This instruction can be used in combination with the LDL instruction to load a register with eight consecutive

bytes from memory, when the bytes cross a doubleword boundary. LDR loads the right portion of the register

with the appropriate part of the low-order doubleword; LDL loads the left portion of the register with the

appropriate part of the high-order doubleword.

The LDR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual

address which can specify an arbitrary byte. It reads bytes only from the doubleword in memory which contains

the specified starting byte. From one to eight bytes will be loaded, depending on the starting byte specified.

Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of

the register; then it loads bytes from memory into the register until it reaches the high-order byte of the

doubleword in memory. The most significant (left-most) byte(s) of the register will not be changed.

address 8

address 0

memory

15 14 13 12 11 10

before

after

$24

LDR $24, 5 ($0)

VR4102 Datasheet(PDF) 598 Page - NEC