VR4102 datasheet(592/701 Pages) NEC

592 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

592

Load Byte

base

1 0 0 0 0 0

offset

26 25

21 20

16 15

Format:

LB rt, offset (base)

Description:

The 16-bit

offset is sign-extended and added to the contents of general register base to form a virtual address.

The contents of the byte at the memory location specified by the effective address are sign-extended and loaded

into general register

rt.

Operation:

vAddr <- ((offset15)

16 || offset15..0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian

mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)

byte <- vAddr2..0 xor BigEndianCPU

GPR [rt] <- (mem7 + 8* byte)

24 || mem

7 + 8* byte..8* byte

vAddr <- ((offset15)

48 || offset

15..0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1..3 || (pAddr2..0 xor ReverseEndian

mem <- LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)

byte <- vAddr2..0 xor BigEndianCPU

GPR [rt] <- (mem7 + 8* byte)

56 || mem

7 + 8* byte..8* byte

Exceptions:

TLB refill exception

TLB invalid exception

Bus error exception

Address error exception

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