VR4102 datasheet(634/701 Pages) NEC

634 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

634

SLLV

Shift Left Logical Variable

SLLV

SPECIAL

0 0 0 0 0 0

0 0 0 0 0

SLLV

0 0 0 1 0 0

26 25

21 20

16 15

11 10

6 5

5555

Format:

SLLV rd, rt, rs

Description:

The contents of general register

rt are shifted left the number of bits specified by the low-order five bits contained

in general register

rs, inserting zeros into the low-order bits.

The result is placed in register

rd.

In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for

all shift amounts, including zero; SLLV with zero shift amount truncates a 64-bit value to 32 bits and then sign

extends this 32-bit value. SLLV, unlike nearly all other word operations, does not require an operand to be a

properly sign-extended word value to produce a valid sign-extended word result.

Operation:

s <- GPR [rs]4...0

GPR [rd] <- GPR [rt](31 - s)...0 || 0

s <- 0 || GPR [rs]4...0

temp <- GPR [rt](31 - s)...0 || 0

GPR [rd] <- (temp31)

32 || temp

Exceptions:

None

Remark SLLV with a shift amount of zero may be treated as a NOP by some assemblers, at some optimization

levels. If using SLLV with a zero shift to truncate 64-bit values, check the assembler you are using.

VR4102 Datasheet(PDF) 634 Page - NEC