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VR4102 Datasheet(PDF) 633 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 633 Page - NEC

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CHAPTER 27 CPU INSTRUCTION SET DETAILS
633
SLL
Shift Left Logical
SLL
0
0 0 0 0 0
SPECIAL
0 0 0 0 0 0
rt
rd
sa
SLL
0 0 0 0 0 0
31
26 25
21 20
16 15
11 10
6 5
0
6
5555
6
Format:
SLL rd, rt, sa
Description:
The contents of general register
rt are shifted left by sa bits, inserting zeros into the low-order bits.
The result is placed in register
rd.
In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for
all shift amounts, including zero; SLL with zero shift amount truncates a 64-bit value to 32 bits and then sign
extends this 32-bit value. SLL, unlike nearly all other word operations, does not require an operand to be a
properly sign-extended word value to produce a valid sign-extended word result.
Operation:
32
T:
GPR [rd] <- GPR [rt]31 - sa...0 || 0
sa
64
T:
s <- 0 || sa
temp <- GPR [rt]31 - s...0 || 0
s
GPR [rd] <- (temp31)
32
|| temp
Exceptions:
None
Remark SLL with a shift amount of zero may be treated as a NOP by some assemblers, at some optimization
levels. If using SLL with a zero shift to truncate 64-bit values, check the assembler you are using.



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