VR4102 datasheet(662/701 Pages) NEC

662 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

662

TLBP

Probe TLB For Matching Entry

TLBP

0 0 0

0 0 0 0

COP0

0 1 0 0 0 0

TLBP

0 0 1 0 0 0

26 25

6 5

619

Format:

TLBP

Description:

The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi

The architecture does not specify the operation of memory references associated with the instruction immediately

after a TLBP instruction, nor is the operation specified if more than one TLB entry matches.

Operation:

Index <- 1 || 0

|| Undefined

for i in 0...TLBEntries - 1

if (TLB [i]95...77 = EntryHi31...13) and (TLB [i]76 or

(TLB [i]71...64 = EntryHi7...0)) then

Index <- 0

26 || i5...0

endif

endfor

Index <- 1 || 0

|| Undefined

for i in 0...TLBEntries - 1

if (TLB [i]167...141 and not (0

15 || TLB [i]216...205))

= (EntryHi39...13) and not (0

15 || TLB [i]216...205)) and

(TLB [i]140 or (TLB [i]135...128 = EntryHi7...0)) then

Index <- 0

26 || i5...0

endif

endfor

Exceptions:

Coprocessor unusable exception

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