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VR4102 Datasheet(PDF) 675 Page - NEC |
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VR4102 Datasheet(HTML) 675 Page - NEC |
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675 / 701 page ![]() CHAPTER 27 CPU INSTRUCTION SET DETAILS 675 Figure 27-1. VR4102 Opcode Bit Encoding (2/2) 23...21 COP0 rs 25, 24 0123 4567 0MF DMF HJ J MT DMT HJ J 1BC JJJ JJJJ 2 3 CO 18...16 COP0 rt 20...19 0123 4567 0 BCF BCT BCFL BCTL JJJJ 1 JJJJ JJJJ 2 JJJJ JJJJ 3 JJJJ JJJJ 2...0 CP0 Function 5...3 0123 4567 0 I TLBR TLBWI II I TLBWR I 1TLBP III IIII 2 [ III IIII 3ERET F III IIII 4 I STANDB SUSPEND HIBERNATE IIII 5 IIII IIII 6 IIII IIII 7 IIII IIII Key: * Operation codes marked with an asterisk cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture. J Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future versions of the architecture. G Operation codes marked with a delta are valid only for VR4102 processors with CP0 enabled, and cause a reserved instruction exception on other processors. I Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in VR4102 implementations. [ Operation codes marked with a xi cause a reserved instruction exception on VR4102 processor. F Operation codes marked with a chi are valid on R4x00 and VR4102 only. H Operation codes marked with epsilon are valid when the processor operating as a 64-bit processor. These instructions will cause a reserved instruction exception if 64-bit operation is not enabled. S Operation codes marked with a pi are invalid and cause coprocessor unusable exception. |
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