VR4102 datasheet(677/701 Pages) NEC

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CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS

The VR4100 CPU core avoids contention of its internal resources by causing a pipeline interlock in such cases as

when the contents of the destination register of an instruction are used as a source in the succeeding instruction.

Therefore, instructions such as NOP must not be inserted between instructions.

However, interlocks do not occur on the operations related to the CP0 registers and the TLB.

Therefore,

contention of internal resources should be considered when composing a program which manipulates the CP0

registers or the TLB. The CP0 hazards define the number of NOP instructions which is required to avoid contention

of internal resources, or the number of instructions unrelated to contention. This chapter describes the CP0 hazards

of the VR4100 CPU core.

The CP0 hazards of the VR4100 CPU core are equally or less stringent than those of the VR4000; Table 28-1 lists

the Coprocessor 0 hazards of the VR4100 CPU core. Code which complies with these hazards will run without

modification on the VR4000.

The contents of the CP0 registers or the bits in the “Source” column of this table can be used as a source after

they are fixed.

The contents of the CP0 registers or the bits in the “Destination” column of this table can be available as a

destination after they are stored.

Based on this table, the number of NOP instructions required between instructions related to the TLB is computed

by the following formula, and so is the number of instructions unrelated to contention:

(Destination Hazard number of A) - [(Source Hazard number of B) + 1]

As an example, to compute the number of instructions required between an MTC0 and a subsequent MFC0

instruction, this is:

(5) - (3 + 1) = 1 instruction

The CP0 hazards do not generate interlocks of pipeline. Therefore, the required number of instruction must be

controlled by program.

VR4102 Datasheet(PDF) 677 Page - NEC