MCP3565R datasheet(19/108 Pages) MICROCHIP

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2020-2021 Microchip Technology Inc.

DS20006401C-page 19

MCP3565R

Note:

Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;

VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.

Histogram ticks are centered at their bin center.

FIGURE 2-37:

SINAD vs. AMCLK

(BOOST = 1x).

FIGURE 2-38:

SINAD vs. AMCLK

(BOOST = 2x).

FIGURE 2-39:

SINAD vs. AMCLK

(BOOST = 0.5x, Internal VREF).

FIGURE 2-40:

SINAD vs. AMCLK

(BOOST = 0.66x, Internal VREF).

FIGURE 2-41:

SINAD vs. AMCLK

(BOOST = 1x, Internal VREF).

FIGURE 2-42:

SINAD vs. AMCLK

(BOOST = 2x, Internal VREF).

100

105

110

AMCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 1x

100

105

110

115

120

AMCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 2x

100

105

MCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 0.5x

100

105

MCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 0.66x

100

105

MCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 1x

100

105

MCLK Frequency (MHz)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

BOOST = 1x

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