MCP3565R datasheet(65/108 Pages) MICROCHIP

65 / 108 page

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DS20006401C-page 65

MCP3565R

6.2.5

FAST COMMANDS DESCRIPTION

There are five possible Fast commands available for the

MCP3565R. For each command, only the COMMAND

byte has to be provided on the SPI port and the

command is executed right after the COMMAND byte

has been clocked. The Fast command codes are

detailed in Table 6-2. All undefined command address

codes for Fast commands will be ignored and will have

no effect. SDO will stay in high-impedance after the

COMMAND byte for a Fast command until a CS rising

edge is provided. The Fast commands can be enabled

or disabled by placing the EN_FASTCMD bit in the IRQ

increase the security of the device because it can avoid

the execution of unwanted Fast commands, which can

be useful in harsh environments.

The ADC Start/Restart command (command address:

‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’,

creating a conversion start (or a restart if the

conversion was already running).

The ADC Standby mode command (command

address: ‘1011’) overwrites the ADC_MODE[1:0] bits

to ‘10’ and places the ADC in Standby mode.

The ADC Shutdown mode command (command

address: ‘1100’) overwrites the ADC_MODE[1:0] bits

to ‘00’ and places the ADC in ADC Shutdown mode.

The Full Shutdown mode command (command

address: ‘1101’) overwrites the CONFIG0 register to

0x00 and places the device in Full Shutdown mode

(see

Section 5.10 “Low-Power Shutdown Modes”

for a full description of this mode).

The Full Reset command (command address: ‘1110’)

resets the device and places the entire register map

into its default state condition, including the

non-writable registers. The only difference with a POR

event is that the POR_STATUS bit in the IRQ register

is set to ‘1’ after a Full Reset and is reset to ‘0’ after a

POR event. The user can only clear the ADC Data

Output register to its default value by using the Full

Reset command.

6.2.6

DEVICE ADDRESS AND STATUS

BYTE DURING CONTROL BYTE

During the COMMAND byte clocking on the SDI pin,

the SDO pin displays a STATUS byte to help the user

retrieve quick interrupt status information.

The STATUS byte allows fast polling of the different

interrupts without having to read the IRQ register.

However, it requires an MCU that can communicate in

Full-Duplex mode (SDI and SDO are clocked at the

same time). For MCUs that are only half-duplex, the

polling of the IRQ status can still be done by reading the

IRQ register continuously.

The STATUS byte structure is described in Figure 6-1.

FIGURE 6-1:

STATUS Byte.

The first two bits are always equal to ‘0’ and SDO

toggles to ‘0’ as soon as a CS pin falling edge is

performed. This allows having an application with

multiple devices, with different device addresses,

sharing one common SPI bus and avoiding bus conten-

tion during STATUS byte clocking.

The next three bits of the STATUS byte give a confirma-

tion (Acknowledge) of the hard-coded device address.

If the device address of the COMMAND byte and the

internal device address of the chip match, these three

bits will be transmitted and they are equal to:

• STAT[5:4] = DEV_ADDR[1:0]

• STAT[3] = DEV_ADDR[0]

The STAT[3] bit allows the user to distinguish the SDO

output from a High-Impedance state (device address is

not matched), as the bits, STAT[4] and STAT[3], are

complementary and will induce a deterministic toggle

on the SDO output.

If the two device address bits are not matched with the

internally hard-coded device address bits, SDO is

maintained in a High-Impedance state during the rest

of the communication and the command is ignored.

This behavior avoids potential bus contention errors if

multiple devices with different device addresses share

the same SPI bus. After the transmission of the first two

bits, only one device responds to the command (all

other devices with non-matching device addresses

keep the SDO in high-impedance). In this case, the

user needs to abort the communication (CS rising

edge) in order to perform another command.

The three LSbs of the STATUS byte are the three

Interrupt Status bits:

• STAT[2] = DR_STATUS (ADC data ready interrupt

status)

• STAT[1] = CRCCFG_STATUS (CRC checksum

error on the register map interrupt status)

• STAT[0] = POR_STATUS (POR interrupt status)

STAT[7]

STAT[6]

STAT[5]

STAT[4]

STAT[3]

STAT[2]

STAT[1]

STAT[0]

DEV_ADDR

[1]

DEV_ADDR

[0]

DEV_ADDR

[0]

DR_ST ATUS

CRCCFG_

ST ATUS

POR_ST ATUS

Device Address

Acknowledge bits

Interrupt Status bits

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