MCP3565R datasheet(16/108 Pages) MICROCHIP

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MCP3565R

DS20006401C-page 16



2020-2021 Microchip Technology Inc.

Note:

Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;

VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.

Histogram ticks are centered at their bin center.

FIGURE 2-19:

SINAD Distribution

Histogram External VREF.

FIGURE 2-20:

THD Distribution Histogram

External VREF.

FIGURE 2-21:

SFDR Distribution

Histogram External VREF.

FIGURE 2-22:

SNR Distribution Histogram

Internal VREF.

FIGURE 2-23:

SINAD Distribution

Histogram Internal VREF.

FIGURE 2-24:

THD Distribution Histogram

Internal VREF.

Signal-to-Noise-and-Distortion Ratio (dB)

33 Devices x 3 Lots

Bin Size: 0.1 dB

Total Harmonic Distortion (dBc)

33 Devices x 3 Lots

Bin Size: 0.5 dB

Spurious-Free Dynamic Range (dBc)

33 Devices x 3 Lots

Bin Size: 1.0 dB

Signal-to-Noise Ratio (dB)

33 Devices x 3 Lots

Bin Size: 0.1 dB

Signal-to-Noise-and-Distortion Ratio (dB)

33 Devices x 3 Lots

Bin Size: 0.1 dB

Total Harmonic Distortion (dBc)

33 Devices x 3 Lots

Bin Size: 0.5 dB

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