MCP3565R datasheet(17/108 Pages) MICROCHIP

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2020-2021 Microchip Technology Inc.

DS20006401C-page 17

MCP3565R

Note:

Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;

VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.

Histogram ticks are centered at their bin center.

FIGURE 2-25:

SFDR Distribution

Histogram Internal VREF.

FIGURE 2-26:

SINAD vs. Temperature,

External VREF.

FIGURE 2-27:

SNR vs. Temperature,

External VREF.

FIGURE 2-28:

THD vs. Temperature,

External VREF.

FIGURE 2-29:

SFDR vs. Temperature,

External VREF.

FIGURE 2-30:

SINAD vs. Temperature,

Internal VREF.

Spurious-Free Dynamic Range (dBc)

33 Devices x 3 Lots

Bin Size: 1.0 dB

100

120

-50

-25

100

125

Temperature (°C)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

100

120

-50

-25

255075

100

125

Temperature (°C)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

-120

-100

-80

-60

-40

-20

-50

-25

255075

100

125

Temperature (°C)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

100

120

140

-50

-25

255075

100

125

Temperature (°C)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

100

120

-50

-25

100

125

Temperature (°C)

GAIN = 0.33

GAIN = 1

GAIN = 2

GAIN = 4

GAIN = 8

GAIN = 16

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