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MCP3565R Datasheet(PDF) 42 Page - Microchip Technology

Part # MCP3565R
Description  Two-Channel, 153.6 ksps, Low Noise 24-Bit Delta-Sigma ADC with Internal Voltage Reference
PDF  108 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3565R Datasheet(HTML) 42 Page - Microchip Technology

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MCP3565R
DS20006401C-page 42
2020-2021 Microchip Technology Inc.
The resolution (number of possible output codes
expressed in powers of two or in bits) of the digital
filter is 24-bit maximum for any OSR = OSR3 x OSR1
and data format choice. The resolution only depends
on the OSR through the OSR[3:0] bits setting in the
CONFIG1 register per Table 5-6. Once the OSR is
chosen, the resolution is fixed and the output code of
the ADC is encoded with the data format defined by
the DATA_FORMAT[1:0] bits setting in the CONFIG3
register.
The transfer function of this filter has a unity gain at
each multiple of DMCLK. A proper anti-aliasing filter
must be placed at the ADC inputs. This will attenuate
the frequency contents around each multiple of
DMCLK and keep the desired accuracy over the base-
band of the converter. This anti-aliasing filter can be a
simple first-order RC network with low time constant to
provide a high rejection at DMCLK frequency.
The conversion time is a function of the OSR settings
and the DMCLK frequency.
EQUATION 5-4:
CONVERSION TIME FOR
OSR = OSR3 x OSR1
In One-Shot mode, each conversion is launched
individually, so the maximum data rate is effectively
1/TCONV if each conversion is launched with no delay.
The digital filter is reset in between each conversion.
However, due to the nature of the digital filter (which
memorizes the sum of the incoming bit stream), the
data rate at the filter output can be maximized if the
filter is never reset. Because of the internal resampling
of the digital filter, the output data rate can be equal to
DMCLK/OSR = DRCLK; this is the case in Continuous
mode. In this case, the first conversion still happens in
the TCONV time, as this is the settling time of the filter.
The subsequent conversions are pipelined and give
their output at a data rate of DRCLK. The Continuous
Conversion mode can optimize the data rate, while
consuming the same power as One-Shot mode, which
is advantageous in applications that require a
continuous sampling of the analog inputs. The
Continuous mode is not compatible with multiplexing
the inputs (see
Section 5.15 “Scan Mode” for more
details about the Conversion mode settings in MUX
and Scan modes).
Figure 5-5 shows the fundamental difference between
One-Shot mode and Continuous mode in a simplified
diagram.
FIGURE 5-5:
One-Shot Mode vs. Continuous Mode.
TCONV
3 OSR3
OSR1 1
–
OSR3
+
DMCLK
=
TCONV
One-shot mode
Conversions are Serialized,
Filter is Reset after Each Conversion
Group Delay: TCONV
Data Rate: 1/(TCONV)
Conversion1
TCONV
Continuous mode
Conversions are Pipelined,
Filter is Never Reset
Group Delay: TCONV
Data Rate: DRCLK
TCONV
Conversion2
TCONV
Conversion3
Conversion3
1/DRCLK
1/DRCLK
TCONV
Analog Input
Signal
Conversion1
Conversion2
TCONV= Settling Time



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