SLG47503 datasheet(39/191 Pages) DIALOG

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Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

39 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Combination Function Macrocells

The SLG47502/03 has 15 combination function macrocells that can serve as more than one logic or timing function. In each case,

they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be

implemented in these macrocells.

 Three macrocells that can serve as 2-bit LUT or as D Flip-Flop, or as Shift Register

 Ten macrocells that can serve as either 3-bit LUTs or as D Flip-Flops with Set/Reset Input, or as Shift Register

 One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGen)

 One macrocell that can serve as either 4-bit LUT or as D Flip-Flop with Set/Reset Input, or as Shift Register

Inputs/Outputs for the 15 combination function macrocells are configured from the connection matrix with specific logic functions

being defined by the state of configuration bits.

When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined

function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).

7.1 2-BIT LUT OR D FLIP-FLOP OR SHIFT REGISTER MACROCELLS

There are three macrocells that can serve as 2-bit LUT or as DFF/LATCH, or as Shift Register. It is also possible to define the

active level (Q or nQ) for the macrocell’s output by registers [748], [753], [758]. DFF/Shift Register or LUT are selected by registers

[744], [749], [754]. When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection matrix

and produce a single output, which goes back into the connection matrix.

When used to implement Shift Register, the two input signals from the connection matrix go to the data (D_in), clock (CLK) inputs

for the Shift Register, with the output going back to the connection matrix. The input data (D_in) writes into LSB. The Shift Register

length (up to 4 bits/memory cells) is selected by registers [746:745], [751:750], [756:755], when these registers = 0 DFF/LATCH

function is selected.

When used to implement DFF/LATCH function, the two input signals from the connection matrix go to the data (D_in), clock (CLK)

inputs for the Flip-Flop, with the output going back to the connection matrix. LATCH or DFF configuration is selected by registers

[747], [752], [757].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is High).

It's possible to read/write the Shift Register content via I2C. See section 15.4.10 for more information.

SLG47503 Datasheet(PDF) 39 Page - Dialog Semiconductor